MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 315

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Bits are ordered first bit left. So, C-channel bit “0” is seen in bit position 31 in the EBURcvCChannel
register. C-channel bit “31” is seen as the LSB bit in the register.
17.6.1.3
When the value of a new IEC958 “C” channel frame is loaded into the EBURcvCChannel register, an
interrupt is generated. This interrupt is cleared when the processor writes the corresponding bit in the
InterruptClear register. EBURcvCChannel is double buffered. However the register can be read at any time
and provide true values the interrupt only indicates that a NEW “C” channel value has been loaded.
17.6.1.4
An interrupt is associated with the Validity flag. (interrupt 24 - IEC958ValNoGood). This interrupt is set
every time a frame is seen on the IEC958 interface with the validity bit set to “invalid”.
17.6.1.5
There are several IEC958 exceptions defined that will trigger an interrupt. These are:
Freescale Semiconductor
Address MBAR2 + 0X24 (EBU1RCVCCHANNEL)
Reset
Reset
•
•
W
W
R
R
Control channel change—Set when EBURcvCChannel register is updated. The register is updated
for every new C-Channel received. The exception is reset when EBURcvCChannel register is read.
EBU Illegal Symbol—Set on reception of illegal symbol during IEC958 receive. Reset by writing
register InterruptClear. Refer to
biphase/mark modulated signal. The time between any two successive transitions of the EBU
signal is always 1, 2 or 3 EBU symbol periods long. The EBU receiver will parse the stream, and
split it in so-called symbols. It recognizes s1, s2 and s3 symbols, depending on the length of the
symbols. Not all sequences of these symbols are allowed. To give an example, a sequence
s2-s1-s1-s1-s2 cannot occur in a error-free EBU signal. If the receiver finds such an illegal
sequence, the illegal symbol interrupt is set. No corrective action is undertaken.
When the interrupt occurs, this means:
a) The EBU signal is has been affected by noise
MBAR2 + 0XD4 (EBU2RCVCCHANNEL)
31
15
–
–
Control Channel Interrupt (IEC958 “C” Channel New Frame)
Validity Flag Reception
IEC958 Exception Definition
30
14
–
–
29
13
–
–
28
12
–
–
Figure 17-9. EBURcvCChannel Register
27
11
–
–
MCF5253 Reference Manual, Rev. 1
Section 17.7.7, “Audio
26
10
–
–
EBURcvC Channel1 and Channel2
EBURcvC Channel1 and Channel2
25
–
–
9
24
–
–
8
23
–
–
7
Interrupts”
22
–
–
6
21
–
–
5
for details. The EBU input is a
20
–
4
–
Audio Interface Module (AIM)
19
–
–
3
Access: User read only
18
–
–
2
17
–
1
–
17-17
16
–
–
0