MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 374

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Background Debug Mode (BDM) Interface
displayed. (debug data: DDATA). The processor status (PST) timing is synchronous with the processor
status clock (PSTCLK) and may not be related to the current bus transfer.
of these signals.
The PST outputs can be used with an external image of the program to completely track the dynamic
execution path of the machine when used with external development systems. The tracking of this dynamic
path is complicated by any change-of-flow operation. This is especially evident when the branch target
address is calculated based on the contents of a program-visible register (variant addressing.) For this
reason, the DDATA outputs can be configured to display the target address of these types of
change-of-flow instructions. Because the DDATA bus is only 4 bits wide, the address is displayed a nibble
at a time across multiple clock cycles.
The debug module includes two 32-bit storage elements for capturing the internal ColdFire bus
information. These two elements effectively form a FIFO buffer connecting the processor’s high-speed
local bus to the external development system through the DDATA signals. The FIFO buffer captures
branch target addresses along with certain operand data values for eventual display on the DDATA output
port, a nibble at a time, starting with the least-significant bit. The execution speed of the ColdFire
processor is affected only when both storage elements contain valid data waiting to be dumped onto the
DDATA port. In this case, the processor core is stalled until one FIFO entry is available. In all other cases,
data output on the DDATA port does not impact execution speed.
20.2.1
The PST signals are encoded to reflect the state of the Operand Execution Pipeline, and are generally not
related to the current external bus transfer.
20.2.1.1
Many instructions complete in a single processor cycle. If an instruction requires more clock cycles, the
subsequent clock cycles are indicated by driving the PST outputs with this encoding.
20.2.1.2
For most instructions, this encoding signals the first clock cycle of an instruction’s execution. Certain
change-of-flow opcodes, plus the PULSE and WDDATA instructions generate different encodings.
20.2.1.3
This encoding indicates the ColdFire processor has entered user mode. This encoding is signaled after the
instruction which caused the user mode entry has executed.
20.2.1.4
The ColdFire instruction set architecture includes a PULSE opcode. This opcode generates a unique PST
encoding, $4, when executed. This instruction can define logic analyzer triggers for debug and/or
performance analysis. Additionally, a WDDATA instruction is supported that allows the processor core to
write any operand (byte, word, longword) directly to the DDATA port, independent of any debug module
20-4
Processor Status Signal Encoding
Continue Execution (PST = $0)
Begin Execution of an Instruction (PST = $1)
Entry into User Mode (PST = $3)
Begin Execution of PULSE or WDDATA instructions (PST = $4)
MCF5253 Reference Manual, Rev. 1
Table 20-1
Freescale Semiconductor
shows the encoding