MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 395

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

DRc encoding:
Command Sequence:
Operand Data:
Longword data is written into the specified debug register. The data is supplied most significant word first.
Result Data:
Command complete status ($0FFFF) is returned when register write is complete.
20.3.4.1.13 Unassigned Opcodes
Unassigned command opcodes are reserved by Freescale. All unused command formats within any
revision level perform a NOP and return the ILLEGAL command response.
20.3.4.2
The presence of rounding logic in the output data path of the eMAC requires special care for
BDM-initiated reads and writes of its programming model. In particular, any result rounding modes must
Freescale Semiconductor
BDM Accesses of the eMAC Registers
DRc[3:0]
$A-$B
$1-$4
$C
$D
$E
$F
$0
$5
$6
$7
$8
$9
WDMREG
Figure 20-26. Write Debug Module Register Command Sequence
???
Configuration/Status
Reserved
BDM Address Attribute
Bus Attributes and Mask
Trigger Definition
PC Breakpoint
PC Breakpoint Mask
Reserved
Operand Address High Breakpoint
Operand Address Low Breakpoint
Data Breakpoint
Data Breakpoint Mask
Table 20-16. Definition of DRc Encoding—Write
Debug Register Definition
MCF5253 Reference Manual, Rev. 1
“Not Ready”
MS Data
“Illegal”
XXX
“Not Ready”
“Not Ready”
Next CMD
LS Data
Mnemonic
PBMR
DBMR
ABHR
BAAR
ABLR
AATR
CSR
DBR
TDR
PBR
–
–
Background Debug Mode (BDM) Interface
“Cmd Complete”
Next CMD
Initial State
$0
$5
$5
$0
–
–
–
–
–
–
–
–
20-25