MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 145

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 9
System Integration Module (SIM)
9.1
This chapter describes the operation, memory map and register descriptions of the System Integration
Module (SIM) registers, including the interrupt controller and system-protection functions for the
MCF5253 processor. The SIM provides overall control of the internal and external buses and serves as the
interface between the ColdFire
configures the general purpose input/output and enables the CPU HALT instruction.
9.1.1
9.2
This chapter provides the SIM register memory map, programming and configuration register
descriptions, interrupt interface register descriptions, secondary interrupt controller register descriptions,
and software interrupts.
Freescale Semiconductor
•
•
•
•
•
•
Module Base Address Registers (MBAR and MBAR2)
— Base address location of all internal peripherals and SIM resources
— Address space masking to internal peripherals and SIM resources
Interrupt Controller
— Two interrupt controllers
— Programmable interrupt level (1–7) for peripheral interrupts
System Protection and Reset Status
— Reset status to indicate cause of last reset
— Software watchdog timer with optional secondary bus monitor functionality
Bus Arbitration Control Register (MPARK)
— Enables display of internal accesses on the external bus for debug
General purpose input/output registers
— Defines general-purpose inputs and outputs
— Edge interrupt triggers on general-purpose I/Os, 0 to 6
Software interrupts
— Allow programmer to make interrupt pending under software control
SIM Overview
SIM Memory Map and Register Definitions
SIM Features
®
core and the internal peripherals or external devices. The SIM also
MCF5253 Reference Manual, Rev. 1
9-1