MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 96

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Address MOVEC with $004
Instruction Cache
5.5.2.2
The access control registers ACR0 and ACR1, provide a definition of memory reference attributes for two
memory regions (one per ACR). This set of effective attributes is defined for every memory reference
using the ACRs or the set of default attributes contained in the CACR. The ACRs are examined for every
memory reference that is NOT mapped to the SRAM module.
The ACRs are 32-bit write-only supervisor control registers. They are accessed in the CPU address space
using the MOVEC instruction with an Rc encoding of $004 and $005. The ACRs can be read when in
background debug mode (BDM). At system reset, the registers are cleared.
5-8
SM1, SM0
Bit Name
Reset
Reset
31–24
23–16
14–13
12–7
BAM
CM
BA
EN
15
6
W
W
R
R
MOVEC with $005
BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BAM31 BAM30 BAM29 BAM28 BAM27 BAM26 BAM25 BAM24
EN
31
15
0
0
The Base Address. An 8-bit field compared to the address bits [31:24] from the processor's local bus under control
of the ACR address mask. If the address matches, the attributes for the memory reference are sourced from the
given ACR.
The Base Address Mask [31:24] 8-bit field can mask any bit of the AB field comparison. If a bit in the AM field is set,
then the corresponding bit of the address field comparison is ignored.
The Enable bit defines the ACR enable. Hardware reset clears this bit, disabling the ACR.
0 ACR disabled
1 ACR enabled
The Supervisor mode two-bit field allows the given ACR to be applied to references based on operating privilege
mode of the ColdFire processor. The field uses the ACR for user references only, supervisor references only, or all
accesses.
00 Match if user mode
01 Match if supervisor mode
1x Match always. Ignore user/supervisor mode
Reserved, should be cleared.
The Cache Mode bit defines the cache mode: 0 is cacheable, 1 is noncacheable.
0 Caching enabled
1 Caching disabled
SM1 SM0
Access Control Registers
30
14
0
0
29
13
0
0
28
12
0
0
Table 5-6. Access Control Registers Field Descriptions
Figure 5-3. Access Control Registers (ACR0, ACR1)
27
11
0
0
26
10
0
0
MCF5253 Reference Manual, Rev. 1
25
0
0
9
24
0
8
0
Description
23
0
0
7
CM
22
0
6
0
BWE
21
0
0
5
20
0
0
4
19
0
3
0
Freescale Semiconductor
Access: User read/write
WP
18
0
0
2
17
0
0
1
16
0
0
0