MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 161

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Notes:
1. INTMON1, INTMON2 registers are used to route an interrupt from the secondary interrupt controller
2. Bits 7–4 of the register can be read to obtain the value of the software interrupts 0
3. Bits 3–0 of the register can be read to read the value of software interrupts 0
4. To write SOFTINT_SET and SOFTINT_CLR registers, while avoiding writing to the INTMONx fields, use word-size or byte-size
9.5
This section provides the system Reset Status register and information about the Software Watchdog Timer
and associated registers and descriptions.
9.5.1
The RSR contains a bit for each reset source to the SIM. A bit set to 1 indicates the last type of reset that
occurred. The RSR is updated by the reset control logic on completion of the reset operation. Only one bit
will be set at any given time in the RSR. If a reset occurs and the user failed to clear this register, reset
control logic will clear all bits and set the appropriate bit to indicate the current cause of reset. The RSR
programming model is illustrated as follows.
The Reset Status Register (RSR) is an 8-bit supervisor read-write register.
9.5.2
The Software Watchdog Timer (SWT) prevents system lockup if the software become trapped in loops
with no controlled exit.
Freescale Semiconductor
SWTR
HRST
Programming
This feature is intended to help measure the latency of an interrupt service routine.
corresponding software interrupt will not change. When written one, the corresponding software interrupt is set to a 1.
corresponding software interrupt will not change. When written one, the corresponding software interrupt is set to 0.
addressing to update only bits 0–7.
Field
Address MBAR + $00
Reset
W
R
System Protection and Reset Status Registers
For the Hardware or System Reset, a 1 = An external device driving RSTI caused the last reset. Assertion of reset
by an external device causes the core processor to take a reset exception. All registers in internal peripherals and
the SIM are reset.
For the Software Watchdog Timer Reset, a 1 = The last reset was caused by the software watchdog timer. If SWRI
in the SYPCR is set and the software watchdog timer times out, a hardware reset occurs.
Reset Status Register
Software Watchdog Timer
HRST
Registers”) such that the interrupt status can be monitored on either the external INTMON1 or INTMON2 pin.
1
7
Table 9-17. Reset Status Register (RSR) Field Descriptions
0
6
Figure 9-9. Reset Status Register (RSR)
MCF5253 Reference Manual, Rev. 1
SWTR
0
5
0
4
Description
0
3
–
3. When written zero, the value of the
–
3. When written zero, the value of the
0
2
System Integration Module (SIM)
(Section 9.3, “SIM Module
Access: User read/write
0
1
0
0
9-17