MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 39

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

1.5
1.5.1
The ColdFire processor Version 2 (CF2) core consists of two independent, decoupled pipeline structures
to maximize performance while minimizing core size.The instruction fetch pipeline (IFP) is a two-stage
pipeline for prefetching instructions. The prefetched instruction stream is then gated into the two-stage
operand execution pipeline (OEP), which decodes the instruction, fetches the required operands, and then
executes the required function. Because the IFP and OEP pipelines are decoupled by an instruction buffer
that serves as a FIFO queue, the IFP can prefetch instructions in advance of their actual use by the OEP,
which minimizes time stalled waiting for instructions. The OEP is implemented in a two-stage pipeline
featuring a traditional RISC data path with a dual-read-ported register feeding an arithmetic/logic unit
(ALU).
1.5.2
The MCF5253 provides four fully programmable DMA channels for quick data transfer. Single and dual
address mode is supported with the ability to program bursting and cycle stealing. Data transfer is
selectable as 8-, 16-, 32-, or 128-bits. Packing and unpacking is supported.
Two internal audio channels and two UART’s can be used with the DMA channels. Any DMA channel
can be used with the ATA interface. All channels can perform memory to memory transfers. The DMA
controller has a user-selectable, 24- or 16-bit counter and a programmable DMA exception handler.
External requests are not supported.
1.5.3
The integrated eMAC unit provides a common set of DSP operations and enhances the integer multiply
instructions in the ColdFire architecture. The eMAC provides functionality in three related areas:
Multiplies of 16x16 and 32x32 with 48-bit accumulates are supported in addition to a full set of extensions
for signed and unsigned integers plus signed, fixed-point fractional input operands. The eMAC has a
single-clock issue for 32x32-bit multiplication instructions and implements a four-stage execution
pipeline.
Freescale Semiconductor
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1. Faster signed and unsigned integer multiplies
2. Multiply-accumulate operations supporting signed and unsigned operands
3. Miscellaneous register operations
— IEEE 1149.1A Test (JTAG) Module
Clocking
— Clock-multiplied PLL, programmable frequency
1.2 V Core, 3.3 V I/O
225 pin BGA package (140 MHz)
MCF5253 Functional Overview
ColdFire CF2 Core
DMA Controller
Enhanced Multiply and Accumulate Module (eMAC)
MCF5253 Reference Manual, Rev. 1
MCF5253 Introduction
1-7