MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 73

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Because ColdFire processors do not support hardware stacking of multiple exceptions, it is the
responsibility of the operating system to check for trace mode after processing other exception types. For
example, consider the execution of a TRAP instruction while in trace mode. The processor will initiate the
TRAP exception and then pass control to the corresponding handler. If the system requires that a trace
exception be processed, it is the responsibility of the TRAP exception handler to check for this condition
(SR[15] in the exception stack frame asserted) and pass control to the trace handler before returning from
the original exception.
3.5.7
This special type of program interrupt is covered in detail in
(BDM) Interface.”
processor does not generate an IACK cycle but rather calculates the vector number internally (vector
number 12).
3.5.8
When an RTE instruction is executed, the processor first examines the 4-bit format field to validate the
frame type. For a ColdFire 5200 processor, any attempted execution of an RTE where the format is not
equal to {4,5,6,7} generates a format error. The exception stack frame for the format error is created
without disturbing the original RTE frame and the stacked PC pointing to the RTE instruction.
The selection of the format value provides some limited debug support for porting code from 68000
applications. On 680x0 family processors, the SR was located at the top of the stack. On those processors,
bit[30] of the longword addressed by the system stack pointer is typically zero. Thus, if an RTE is
attempted using this “old” format, it generates a format error on a ColdFire 5200 processor.
If the format field defines a valid type, the processor: (1) reloads the SR operand, (2) fetches the second
longword operand, (3) adjusts the stack pointer by adding the format value to the auto-incremented address
after the fetch of the first longword, and then (4) transfers control to the instruction address defined by the
second longword operand within the stack frame.
3.5.9
Executing TRAP always forces an exception and is useful for implementing system calls. The trap
instruction may be used to change from user to supervisor mode.
3.5.10
The interrupt exception processing, with interrupt recognition and vector fetching, includes uninitialized
and spurious interrupts as well as those where the requesting device supplies the 8-bit interrupt vector.
Autovectoring may optionally be supported through the System Integration module (SIM).
Freescale Semiconductor
Debug Interrupt
RTE and Format Error Exceptions
TRAP Instruction Exceptions
Interrupt Exception
This exception is generated in response to a hardware breakpoint register trigger. The
MCF5253 Reference Manual, Rev. 1
Chapter 20, “Background Debug Mode
ColdFire Core
3-11