MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 481

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor
Field
URI
SRI
AAI
SEI
FRI
PCI
SLI
8
7
6
5
4
3
2
Table 24-16. USB Status Register (USBSTS) Register Field Descriptions (continued)
DCSuspend. This is a non-EHCI bit that is present on the USB OTG module only. When a device controller
enters a suspend state from an active state, this bit is set. The device controller clears the bit upon exiting from
a suspend state. Used only by the device controller.
1 Suspended.
0 Active.
Host mode:
This is a non-EHCI status bit. In host mode, this bit will be set every 125us, provided the PHY clock is present
and running (for example, the port is NOT suspended), and can be used by the host controller driver as a time
base.
Device mode:
SOF Received. When the controller detects a Start Of (micro) Frame, this bit will be set. When a SOF is
extremely late, the controller will automatically set this bit to indicate that an SOF was expected. Therefore, this
bit will be set roughly every 1 msec in device FS mode and every 125 msec in HS mode and will be
synchronized to the actual SOF that is received. Since the controller is initialized to FS before connect, this bit
will be set at an interval of 1 msec during the prelude to the connect and chirp.
The software writes a 1 to this bit to clear it.
USB Reset Received. This is a non-EHCI bit that is present on the USB OTG module only. When the controller
detects a USB Reset and enters the default state, this bit will be set. The software can write a 1 to this bit to
clear the USB Reset Received status bit. Used only in device mode.
1 Reset received.
0 No reset received.
Interrupt on Async Advance. The system software can force the controller to issue an interrupt the next time
the controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell
bit in the USBCMD register. This status bit indicates the assertion of that interrupt source. Used only in host
mode.
1 Async advance interrupt.
0 No async advance interrupt.
System Error. This bit is set whenever an error is detected on the system bus. If the System Error Enable (SEE)
bit in the USBINTR is set, an interrupt will be generated. The interrupt and status bits will remain asserted until
cleared by writing a 1 to this bit. Additionally, when in host mode, the RUN/STOP (RS) bit of the USBCMD
register is cleared, effectively disabling the controller. For the controller in device mode, an interrupt is
generated, but no other action is taken.
1 Error.
0 Normal operation.
Frame List Rollover. The controller sets this bit to a one when the Frame List Index rolls over from its maximum
value to zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the
frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index
Register rolls over every time FRINDEX [1 3] toggles. Similarly, if the size is 512, the controller sets this bit to
a one every time FHINDEX [12] toggles. Used only in host mode.
Host mode:
Port Change Detect. The controller sets this bit to a one when on any port a Connect Status occurs, a Port
Enable/Disable Change occurs, an Over Current Change occurs, or the Force Port Resume bit is set as the
result of a J-K transition on the suspended port.
Device mode:
The controller sets this bit to a one when it enters the full or high-speed operational state. When the it exits the
full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB
Reset Received bit and the DCSuspend bits respectively.
This bit is not EHCI compatible.
MCF5253 Reference Manual, Rev. 1
Description
Universal Serial Bus Interface
24-19