MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 640

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

FlexCAN Module
25.6.4
The matching process is an algorithm that scans the entire MB memory looking for Rx MBs programmed
with the same ID as the one received from the CAN bus. Only MBs programmed to receive will participate
in the matching process for received frames.
While the ID, DLC and data fields are retrieved from the CAN bus, they are stored temporarily in the serial
message buffer
during the CRC field. If a matching ID is found in one of the MBs, the contents of the SMB will be
transferred to the matched MB during the sixth bit of the end-of-frame field of the CAN protocol. This
operation is called ‘move-in.’ If any protocol error (CRC, ACK, etc.) is detected, than the move-in
operation does not happen.
An MB with a matching ID is free to receive a new frame if the MB is not locked (see
“Locking and Releasing Message
the CPU has already serviced the MB (read the C/S word and then unlocked the MB).
Matching to a range of IDs is possible by using ID acceptance masks (RXGMASK n , RX14MASK n , and
RX15MASK n ). During the matching algorithm, if a mask bit is asserted, then the corresponding ID bit is
compared. If the mask bit is negated, the corresponding ID bit is ‘don’t care.’
25.6.5
In order to maintain data coherency and FlexCAN proper operation, the CPU must obey the rules described
in
a MB structure within FlexCAN other than those specified may cause FlexCAN to behave in an
unpredictable way.
25.6.5.1
To allow double buffering of messages, the FlexCAN has two shadow buffers called serial message
buffers. These two buffers are used by the FlexCAN for buffering both received messages and messages
to be transmitted. Only one SMB is active at a time, and its function depends upon the operation of the
FlexCAN at that time. At no time does the user have access to or visibility of these two buffers.
25.6.5.2
If the CPU wants to change the function of an active MB, the recommended procedure is to put the module
into freeze mode and then change the CODE field of that MB. This is a safe procedure because the
FlexCAN waits for pending CAN bus and MB moving activities to finish before entering freeze mode.
Nevertheless, a mechanism is provided to maintain data coherence when the CPU writes to the control and
status word of active MBs out of freeze mode.
Any CPU write access to the C/S word of an MB causes that MB to be excluded from the transmit or
receive processes during the current matching or arbitration round. This mechanism is called MB
deactivation. It is temporary, affecting only for the current match/arbitration round.
25-24
Section 25.6.1, “Transmit Process”
Matching Process
Message Buffer Handling
Serial Message Buffers (SMBs)
Message Buffer Deactivation
(Section 25.6.5.1, “Serial Message Buffers
Buffers”). The CODE field is either EMPTY, FULL, or OVERRUN but
MCF5253 Reference Manual, Rev. 1
and
Section 25.6.3, “Receive Process.”
(SMBs)”). The matching process takes place
Any form of CPU accessing
Freescale Semiconductor
Section 25.6.5.3,