MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 379

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

20.3.2.1
The basic receive packet of information is 17 bits long,16 data bits plus a status bit, as shown in
Figure
Table 20-2
20.3.2.2
The basic transmit packet of information is 17 bits long,16 data bits plus a control bit, as shown in
Figure
Freescale Semiconductor
Data Field
C-Control
S-Status
Field
15–0
Field
15–0
Data
16
16
20-4.
20-5.
describes the receive BDM packets. Bit descriptions are described in
Receive Packet Format
Transmit Packet Format
The Control Bit (Bit 16) is reserved. Command and data transfers initiated by the development system should
clear bit 16.
The data field contains the message data to be communicated from the development system to the debug
module.
The status bit indicates the status of CPU-generated messages as shown in
system. The response message is always a single word, with the data field encoded as shown in
The data field contains the message data to be communicated from the debug module to the development
16
S
16
C
Table 20-4. Transmit BDM Packet Register Field Descriptions
Table 20-3. Receive BDM Packet Register Field Descriptions
S Bit
15
0
0
1
1
1
15
Table 20-2. CPU-Generated Command Responses
14
14
Figure 20-5. Transmit BDM Packet Register
Figure 20-4. Receive BDM Packet Register
13
13
12
MCF5253 Reference Manual, Rev. 1
12
$FFFF
$FFFF
$0000
$0001
Data
xxxx
11
11
10
10
DATA FIELD [15:0]
9
DATA FIELD [15:0]
9
Valid data transfer
Error—terminated bus cycle; data invalid
Status OK
Not ready with response; try again
Illegal command
8
8
Description
Description
7
7
6
6
Message Type
5
5
4
4
3
3
Background Debug Mode (BDM) Interface
2
2
1
Table
1
Table
0
0
20-2.
20-3.
Table
20-2.
20-9