MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 410

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Background Debug Mode (BDM) Interface
For BDM commands that access memory, the debug module requests the processor’s local bus. The
processor responds by stalling the instruction fetch pipeline and then waiting until all current bus activity
is complete. At that time, the processor relinquishes the local bus to allow the debug module to perform
the required operation. After the conclusion of the debug module bus cycle, the processor reclaims
ownership of the bus.
The development system must use caution in configuring the breakpoint registers if the processor is
executing. The debug module does not contain any hardware interlocks, so Freescale recommends that the
TDR be disabled while the breakpoint registers are being loaded. At the conclusion of this process, the
TDR can be written to define the exact trigger. This approach guarantees that no spurious breakpoint
triggers occur.
Because there are no hardware interlocks in the debug unit, no BDM operations are allowed while the CPU
is writing the debug’s registers (BKPT and DSCLK must be inactive).
20.5.9
The ColdFire BDM connector is a 26-pin Berg Connector arranged 2x13, shown in
20-40
•
•
Read/Write Address and Data Registers
Read/Write Control Registers
Freescale-Recommended BDM Pinout
1
2
Developer Reserved
Freescale Reserved
Supplied by target
Pins reserved for BDM developer use. Contact developer.
Vdd_CPU
DDATA2
DDATA0
RESET
+3.3V
PST2
PST0
Figure 20-39. Recommended BDM Connector
GND
GND
GND
GND
1
1
MCF5253 Reference Manual, Rev. 1
1
3
5
7
9
11
13
15
17
19
21
23
25
10
12
14
16
18
20
22
24
26
2
4
6
8
BKPT
DSCLK
Developer Reserved
DSI
DSO
PST3
PST1
DDATA3
DDATA1
GND
Freescale Reserved
PSTCLK
TA
Figure
Freescale Semiconductor
2
20-39.