MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 356

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

I
18.5.5
When an address and R/W bit is written to the MBDR and the I
When data is written to the MBDR, a data transfer is initiated. The most significant bit is sent first in both
cases. In the master-receive mode, reading the MBDR register allows the read to occur but also initiates
next byte data receiving. In slave mode, the same function is available after it is addressed.
18.6
18.6.1
A reset places the I
users must perform an initialization procedure as follows:
18-12
2
Address MBAR+$290 (MBDR)
RXAK
C Modules
Field
IIF
Reset
1
0
1. Update the Frequency Divider Register (MFDR) and select the required division ratio to obtain
2. Update the I
3. Set the IEN bit of the I
4. Modify the MBCR to select master/slave mode, transmit/receive mode, and interrupt-enable or not.
W
R
SCL frequency from the system bus clock.
The I
IIEN is set). IIF is set when one of the following events occurs:
This bit must be cleared by software by writing a zero to it in the interrupt routine.
The value of SDA during the acknowledge bit of a bus cycle. If the received acknowledge bit (RXAK) is low, it indicates
an acknowledge signal has been received after the completion of 8 bits data transmission on the bus. If RXAK is high,
it means no acknowledge signal has been detected at the 9th clock.
1 No acknowledge received
0 Acknowledge received
• Complete one byte transfer (set at the falling edge of the 9th clock)
• Receive a calling address that matches its own specific address in slave-receive mode
• Arbitration lost
MBAR2+$450 (MBDR2)
I
2
2
I
C Programming Examples
Initialization Sequence
C Interrupt (IIF) bit is set when an interrupt is pending, which will cause a processor interrupt request (provided
2
D7
0
7
C Data I/O Registers (MBDR)
2
2
C Control Register into default status. Before the interface can transfer serial data,
C Address Register (MADR) to define its slave address.
D6
0
6
Table 18-6. MBSR Register Field Descriptions
2
C Control Register (MBCR) to enable the I
MCF5253 Reference Manual, Rev. 1
D5
0
5
Figure 18-8. MBDR Register
D4
0
4
Description
D3
3
0
2
C is the master, a transmission will start.
Access: Supervisor or User read/write
D2
0
2
2
C bus interface system.
Freescale Semiconductor
D1
0
1
D0
0
0