MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 539

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

will automatically execute the value of Mult transactions. The host controller will not execute all Mult
transactions if:
24.9.8.2
A client buffer request to an isochronous endpoint may span 1 to N micro-frames. When N is larger than
one, the system software may have to use multiple iTDs to read or write data with the buffer (if N is larger
than eight, it must use more than one iTD).
Figure 24-48
periodic schedule (that is, the periodic frame list and a set of iTDs). On the right is the client description
of its request. The description includes a buffer base address plus additional annotations to identify which
portions of the buffer should be used with each bus transaction. In the middle is the iTD data structures
used by the system software to service the client request. Each iTD can be initialized to service up to 24
transactions, organized into eight groups of up to three transactions each. Each group maps to one
micro-frame's worth of transactions. The EHCI controller does not provide per-transaction results within
a micro-frame. It treats the per-micro-frame transactions as a single logical transfer. On the left is the host
controller’s frame list. The system software establishes references from the appropriate locations in the
frame list to each of the appropriate iTDs. If the buffer is large, then the system software can use a small
set of iTDs to service the entire buffer. The system software can activate the transaction description records
(contained in each iTD) in any pattern required for the particular data stream.
Freescale Semiconductor
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•
The endpoint is an OUT and Transaction n Length goes to zero before all the Mult transactions
have executed (ran out of data), or
The endpoint is an IN and the endpoint delivers a short packet, or an error occurs on a transaction
before Mult transactions have been executed. The end of micro-frame may occur before all of the
transaction opportunities have been executed. When this happens, the transfer state of the transfer
description is advanced to reflect the progress that was made, the result written back to the iTD and
the host controller proceeds to processing the next micro-frame.
Software Operational Model for iTDs
illustrates the simple model of how a client buffer is mapped by the system software to the
MCF5253 Reference Manual, Rev. 1
Universal Serial Bus Interface
24-77