MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 347
MCF5253CVM140
Manufacturer Part Number
MCF5253CVM140
Description
IC MPU 32BIT 140MHZ 225-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF525xr
Datasheets
1.MCF5253VM140J.pdf
(34 pages)
2.MCF5253VM140J.pdf
(8 pages)
3.MCF5253VM140J.pdf
(648 pages)
4.MCF5253VM140J.pdf
(2 pages)
Specifications of MCF5253CVM140
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
140MHz
Connectivity
CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
Peripherals
DMA, WDT
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
225-MAPBGA
Family Name
MCF5xxx
Device Core
ColdFire V2
Device Core Size
32b
Frequency (max)
140MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.2/3.3V
Operating Supply Voltage (max)
1.32/3.6V
Operating Supply Voltage (min)
1.08/3V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
225
Package Type
MA-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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- MCF5253VM140J PDF datasheet
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of the I
issues in some systems.
The I
corruption if two or more masters attempt to control the bus simultaneously. This feature allows for
complex applications with multiprocessor control. It can also be used for rapid testing and alignment of
end products using external connections to an assembly line computer.
18.3
I
connected to these two signals must have open drain or open collector outputs. The logic AND function is
exercised on both lines with external pullup resistors.
The default state of I
responding to a slave transmit address, the I
receiver.
18.4
A standard communication is composed of four parts:
They are described briefly in the following sections and shown in
Freescale Semiconductor
2
C module uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices
1. START signal
2. Slave address transmission
3. Data transfer
4. STOP signal
2
C system is a true multimaster bus including collision detection and arbitration that prevents data
2
C pull-up resistors will need to be kept at a relatively low impedance, which may cause noise
I
I
2
2
C System Configuration
C Protocol
This I
from Philips. For further information on I
and restrictions please refer to the Philips I
2
2
C is as a slave receiver out of reset. Thus, when not programmed to be a master or
C module is designed to be compatible with the I
MCF5253 Reference Manual, Rev. 1
2
C module should always return to the default state of slave
NOTE
2
C system configuration, protocol,
2
C Standard.
Figure
2
C bus protocol
18-2.
I
2
C Modules
18-3
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