MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 209

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

13.4
The MCF5253 is capable of interfacing with Sony Memory Stick and Multi-Media Card (MMC) / Secure
Digital (SD) flash cards. The interface can handle one of them at any given time, but not both at the same
time.
In the Flash Media interface there are four blocks:
Each interface shift register is a serial interface to the Flash Media device. The two interfaces share the
clock generating circuitry.
The flash media interface can operate in two modes.
Freescale Semiconductor
1. The clock generator generates the clock to the flash device
2. The Processor interface handles interrupts and processor I/O
3. Interface shift register 1
4. Interface shift register 2
1. MemoryStick mode. In this mode it is possible to connect two Sony Memory Stick cards. Each
interface can handle one Memory Stick card. The two interfaces share only the clock generating
logic, all other logic is fully independent.
Flash Media Interface
If CS2POST is set to 2, every write cycle is lengthened with 1 clock. If
CS2POST is set to 3, every write cycle is lengthened with 2 clocks. This
marginally reduces throughput.
A 3-clock cycle hold time to any MCF5253 external access has been added.
As a result, hold time address to TA and write data to TA is not an issue.
Clock
Generator
Processor
Interface
Figure 13-8. Flash Media Block Diagram
stopclock1
stopclock2
MCF5253 Reference Manual, Rev. 1
Interface shift
register 1
NOTE
NOTE
Interface shift
register 2
SCLKOUT
SDATA2
SDATA0_SDIO1
BS2
CMD_SDIO2
BS1
SDATA3
SDATA1
sclk_out_pin
bs1_pin
sdata3_pin
sdata2_pin
sdata1_pin
sdata0_sdio1_pin
bs2_pin
cmd_sdio2_pin
IDE and Flash Media Interface
13-11