MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 247

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 15
UART Modules
This chapter provides signal descriptions, operation, memory map, and register descriptions, an
initialization sequence of the three UART modules.
The MCF5253 contains three asynchronous receiver/transmitters (UARTs) that act independently. Each
UART is clocked by the system clock. This chapter applies to all three UARTs, which are functionally
identical. Refer to
differences.
Each UART module, shown in
15.1
The MCF5253 contains three independent UART modules. Features of each UART module include the
following:
Freescale Semiconductor
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Serial Communication Channel
16-Bit Baud-Rate Timer
Internal Channel Control Logic
Interrupt Control Logic
UART clocked by the system clock
Full duplex asynchronous receiver/transmitter channel
Quadruple-buffered receiver
Double-buffered transmitter
UART Module Features
Section 15.4, “UART Memory Map and Register Definitions,”
FOR BAUD RATE GENERATION
SERIAL COMMUNICATION
16-BIT TIMER
Figure
INTERRUPT CONTROL
INTERNAL CHANNEL
CONTROL LOGIC
CHANNEL
Figure 15-1. UART Block Diagram
MCF5253 Reference Manual, Rev. 1
LOGIC
15-1, consists of the following functional areas:
CTS (UART0/1 only)
RTS (UART0/1 only)
RXD
TXD
SYSTEM CLOCK
for addressing
15-1