MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 536

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Universal Serial Bus Interface
24.9.7
The periodic schedule traversal is enabled or disabled via the Periodic Schedule Enable bit in the
USBCMD register. If the Periodic Schedule Enable bit is cleared, then the host controller simply does not
try to access the periodic frame list via the PERIODICLISTBASE register. Likewise, when the Periodic
Schedule Enable bit is a one, then the host controller does use the PERIODICLISTBASE register to
traverse the periodic schedule. The host controller will not react to modifications to the Periodic Schedule
Enable immediately. In order to eliminate conflicts with split transactions, the host controller evaluates the
Periodic Schedule Enable bit only when FRINDEX[2:0] is zero. The system software must not disable the
periodic schedule if the schedule contains an active split transaction work item that spans the 0b000
micro-frame. These work items must be removed from the schedule before the Periodic Schedule Enable
bit is cleared. The Periodic Schedule Status bit in the USBSTS register indicates status of the periodic
schedule. The system software enables (or disables) the periodic schedule by setting (or clearing) the
Periodic Schedule Enable bit in the USBCMD register. The software then can poll the Periodic Schedule
Status bit to determine when the periodic schedule has made the desired transition. The software must not
modify the Periodic Schedule Enable bit unless the value of the Periodic Schedule Enable bit equals that
of the Periodic Schedule Status bit.
The periodic schedule is used to manage all isochronous and interrupt transfer streams. The base of the
periodic schedule is the periodic frame list. The software links schedule data structures to the periodic
frame list to produce a graph of scheduled data structures. The graph represents an appropriate sequence
of transactions on the USB.
period of one are linked directly to the periodic frame list. Interrupt transfers (are managed with queue
heads) and isochronous streams with periods other than one are linked following the period-one
iTD/siTDs. Interrupt queue heads are linked into the frame list ordered by poll rate. Longer poll rates are
linked first (for example, closest to the periodic frame list), followed by shorter poll rates, with queue
heads with a poll rate of one, on the very end.
24-74
FRINDEX[13:3]
Periodic Schedule
N+1
N+1
N+1
N+1
N+1
N+1
N+1
N
Table 24-64. Operation of FRINDEX and SOFV (SOF Value Register)
Current
SOFV
N+1
N+1
N+1
N+1
N+1
N+1
Figure 24-47
N
N
MCF5253 Reference Manual, Rev. 1
FRINDEX[2:0]
illustrates isochronous transfers (using iTDs and siTDs) with a
111
000
001
010
011
100
101
110
FRINDEX[13:3]
N+1
N+1
N+1
N+1
N+1
N+1
N+1
N+1
SOFV
Next
N+1
N+1
N+1
N+1
N+1
N+1
N+1
N
Freescale Semiconductor
FRINDEX[2:0]
000
001
010
011
100
101
110
111