MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 407

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor
Reset
Reset
STATUS
31–28
23–20
BKPT
HALT
Field
TRG
PCD
FOF
HRL
BKD
27
26
25
24
18
17
W
W
R
R
MAP
31
15
Note:
0
0
The Breakpoint Status 4-bit field provides read-only status information concerning the hardware breakpoints.
This field is defined as follows:
000x No breakpoints enabled
001x Waiting for level 1 breakpoint
010x Level 1 breakpoint triggered
101x Waiting for level 2 breakpoint
110x Level 2 breakpoint triggered
The breakpoint status is also output on the DDATA port when it is not busy displaying other processor data. A
write to the TDR resets this field.
If the read-only Fault-on-Fault status bit is set, a catastrophic halt has occurred and forced entry into BDM.
This bit is cleared on a read from the CSR.
If the read-only Hardware Breakpoint Trigger status bit is set, a hardware breakpoint has halted the processor
core and forced entry into BDM. This bit is cleared by reading CSR.
If the read-only Processor Halt status bit is set, the processor has executed the HALT instruction and forced
entry into BDM. This bit is cleared by reading the CSR.
If the read-only Breakpoint Assert status bit is set, the BKPT signal was asserted, forcing the processor into
BDM. This bit is cleared on a read from the CSR.
This hardware revision level indicates the level of functionality implemented in the debug module. This
information could be used by an emulator to identify the level of functionality supported. A zero value would
indicate the initial debug functionality. For example, a value of 1 would represent Revision A while a value of
0 would represent the earlier release of Revision A.
The Disable the Normal BKPT Input Signal Functionality bit is used to disable the normal BKPT input signal
functionality, and allow the assertion of this pin to generate a debug interrupt. If set, the assertion of the BKPT
pin is treated as an edge-sensitive event. Specifically, a high-to-low edge on the BKPT pin generates a signal
to the processor indicating a debug interrupt. The processor makes this interrupt request pending until the
next sample point occurs. At that time, the debug interrupt exception is initiated. In the ColdFire architecture,
the interrupt sample point occurs once per instruction. There is no support for any type of “nesting” of debug
interrupts.
If set, the PSTCLK Disable bit disables the generation of the PSTCLK output signal, and forces this signal to
remain quiescent.
TRC
The CSR is a write only register from the programming model. It can be read from and written to through the BDM port.
30
14
0
0
STATUS
Table 20-22. Configuration/Status Register (CSR) Field Descriptions
EMU
29
13
0
0
Figure 20-37. Configuration/Status Register (CSR)
28
12
0
0
DDC
FOF
27
11
0
0
MCF5253 Reference Manual, Rev. 1
TRG
UHE
26
10
0
0
HALT
25
0
0
9
BTB
BKPT
24
0
0
8
Description
23
–
0
7
NPL
22
–
0
6
HRL
IPI
21
–
0
5
Background Debug Mode (BDM) Interface
SSM
20
–
0
4
19
–
–
3
Access: User read/write
BKD
18
–
2
–
PCD
17
–
–
1
20-37
IPW
16
0
–
0