MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 474

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Universal Serial Bus Interface
24.6.2.3
This register contains structural parameters such as the number of downstream ports.
the HCSPARAMS register.
Table 24-11
24.6.2.4
This register identifies multiple mode control (time-base bit functionality) addressing capability.
Figure 24-11
24-12
N_PORTS
Address MBAR2 + 0x704
N_PCC
N_PTT
31–28
27–24
23–20
19–17
15–12
N_CC
N_TT
Field
11–8
Reset
Reset
PPC
7–5
3–0
16
PI
4
W
W
R
R
Table 24-11. Host Controller Structural Parameters (HCSPARAMS) Register Field Descriptions
31
15
0
0
Reserved.
Number of transaction translators. This is a non-EHCI field. This field indicates the number of embedded transaction
translators associated the module. This field is always 1.
Ports per transaction translator. This is a non-EHCI field. (EHCI defines this field as optional debug port number.
DMcQ) The number of ports assigned to each transaction translator. This will always be equal to 1.
Reserved.
Port indicators. This bit indicates whether the ports support port indicator control. Always 1.
1 The port status and control registers include a r/w field for controlling the state of the port indicator.
Number of Companion Controllers. This field indicates the number of companion controllers associated with the
controller. This field is always 0.
Number Ports per CC. This field indicates the number of ports supported per internal companion controller. This
field is always 0.
Reserved.
Power Port Control. This bit indicates whether the host controller supports port power control. It is always 1.
1 Ports have power port switches.
Number of Ports. This field indicates the number of physical downstream ports implemented for host applications.
The value of this field determines how many port registers are addressable in the operational register. Always 0x1.
provides bit descriptions for the HCSPARAMS register.
Host Controller Structural Parameters (HCSPARAMS)
Host Controller Capability Parameters (HCCPARAMS)
shows the HCCPARAMS register.
Figure 24-10. Host Controller Structural Parameters (HCSPARAMS) Register
30
14
0
0
N_CC
29
13
0
0
28
12
0
0
27
11
0
0
MCF5253 Reference Manual, Rev. 1
26
10
0
0
N_PCC
N_TT
25
0
0
9
Description
24
0
0
8
23
0
0
7
22
0
0
6
N_PTT
21
0
0
5
PPC
20
0
1
4
19
0
0
3
Freescale Semiconductor
Figure 24-10
N_PORTS
18
Access: User read
0
0
2
17
0
0
1
shows
16
PI
1
1
0