MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 475

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Table 24-12
Freescale Semiconductor
Address MBAR2 + 0x708
31–16 Reserved.
EECP
Field
15–8
ADC
ASP
PFL
7–4
IST
Reset
Reset
3
2
1
0
W
W
R
R
Table 24-12. Host Control Capability Parameters (HCCPARAMS) Register Field Descriptions
EHCI Extended Capabilities Pointer. This optional field indicates the existence of a capabilities list. A value of 0x00
indicates no extended capabilities are implemented. A non-zero value in this register indicates the offset in PCI
configuration space of the first EHCI extended capability. The pointer value must be 0x40 or greater if implemented to
maintain the consistency of the PCI header defined for this class of device.
This field is always 0.
Isochronous Scheduling Threshold. This field indicates, relative to the current position of the executing host controller,
where the software can reliably update the isochronous schedule. When bit [7] is zero, the value of the least significant
3 bits indicates the number of microframes a host controller can hold a set of isochronous data structures (one or more)
before flushing the state. When bit [7] is a one, then the host software assumes the host controller may cache an
isochronous data structure for an entire frame.
This field is always 0.
Reserved.
Asynchronous Schedule Park Capability. This bit indicates if the host controller supports the park feature for high-speed
queue heads in the Asynchronous Schedule. The feature can be disabled or enabled and set to a specific level by using
the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD
register.
This field is always 1(park feature supported).
Programmable Frame List Flag. This bit indicates that the system software can specify and use a frame list length less
that 1024 elements. Frame list size is configured via the USBCMD register Frame List Size field. The frame list must
always be aligned on a 4K page boundary. This requirement ensures that the frame list is always physically contiguous.
This field is always 1.
64-bit Addressing Capability. This field is always 0; 64-bit addressing is not supported.
0 Data structures use 32-bit address memory pointers
31
15
0
0
provides bit descriptions for the HCCPARAMS register.
30
14
Figure 24-11. Host Control Capability Parameters (HCCPARAMS) Register
0
0
29
13
0
0
28
12
0
0
EECP
27
11
0
0
MCF5253 Reference Manual, Rev. 1
26
10
0
0
25
0
0
9
Description
24
0
0
8
23
0
0
7
22
0
0
6
IST
21
0
0
5
20
0
0
4
Universal Serial Bus Interface
19
0
0
3
ASP
18
Access: User read
0
1
2
PFL
17
0
1
1
ADC
24-13
16
0
0
0