MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 368

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Boot ROM
will scale in a linear fashion with lower clock frequencies. Obviously the boot time will increase with
lower frequencies, but the interface will still operate.
The loader uses ‘sequential read mode’ to retrieve the data, and starts reading from address zero.
Boot from a serial device over the SPI interface is similar to the I
maximum bit rate is used, which is dependent on the clock input. QSPI_CS0, QSPI_DIN, QSPI_DOUT
and QSPI_CLK provide the interface to the external device.
19.2.5.2
In I
the slave address 0b0101000x.
19.2.5.3
In UART mode, the MCF5253 acts as a slave device and receives data over UART1 (TXD1 and RXD1).
UART configuration:
Baud rate:19200 / 9600 / 4800 baud @ Xtal = 33.8688 / 16.9344 / 8.4672 MHz (see config GPIO’s)
Bits:
Parity
Stop Bits1
19.2.5.3.1
To allow a master device to synchronize with the MCF5253 during the boot process, the boot loader will
echo all data received from the master. Data bytes are echoed as they are received. The master can use the
echo to determine if the data has been received correctly or determine when an execute command has been
completed.
19.2.5.4
The boot loader expects a partitioned disk, with the first partition being a FAT32 partition.
19-6
2
C slave mode, an external master can transfer boot records and data to the boot loader via I2C0, using
19200 / 9600 baud @ Xtal = 11.2896 / 5.6448 MHz (see config GPIO’s)
19200 / 9600 / 4800 baud @ Xtal = 20 / 10 / 5 MHz (see config GPIO’s)
8
None
Boot from I
Boot from UART
Boot from IDE Device
The baud rate generator must be configured such that the actual baud rate is
within +/- 3% of the intended baud rate.
UART Protocol
2
C - Slave Mode
Figure 19-1. I
MCF5253 Reference Manual, Rev. 1
2
NOTE
C Master Boot Mode
2
C master mode. In SPI mode the
16-bit addressing mode
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