MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 154

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

System Integration Module (SIM)
9.4.1.1
The IMR register is used to mask both internal and external interrupt sources from occurring.
9.4.1.2
9-10
Address MBAR + 0x44
The IPR makes visible the interrupt sources that have an interrupt pending.
31–18
Reset
Reset
Field
17–8
IMR
7–0
W
W
R
R
DMA1 DMA0 UART1 UART0 I
31
15
Reserved.
Each Interrupt Mask bit corresponds to an interrupt source defined in the Interrupt Control Register (ICR). An
interrupt is masked by setting the corresponding bit in the IMR. When a masked interrupt occurs, the corresponding
bit in the IPR is still set, regardless of the setting of the IMR bit, but no interrupt request is passed to the core
processor. At system reset, all defined bits are initialized high, thereby masking all interrupts.
The proper procedure for masking interrupt sources is to first set the core’s status register interrupt mask level to
the level of the source being masked in the IMR. Then, the IMR bit can be masked.
An interrupt can be masked by setting the corresponding bit in the IMR and enable an interrupt by clearing the
corresponding bit in the IMR.
Reserved.
–
1
Interrupt Mask Register
Interrupt Pending Register
30
14
–
1
29
13
–
1
Table 9-9. Interrupt Mask Register (IMR) Field Descriptions
28
12
–
1
Figure 9-5. Interrupt Mask Register (IMR)
2
27
11
–
C0 TIMER1 TIMER0 SWT
1
MCF5253 Reference Manual, Rev. 1
26
10
–
1
25
–
1
9
Description
24
–
1
8
23
–
1
7
22
–
1
6
21
–
1
5
20
–
1
4
19
–
1
3
Freescale Semiconductor
Access: User read/write
QSPI DMA3
18
1
1
2
17
1
1
1
DMA2
16
1
0
–