MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 44

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

MCF5253 Introduction
1.5.25
Up to 60 General Purpose Inputs and up to 57 General Purpose Outputs are available. These are
multiplexed with various other signals. Seven of the GPIO inputs have edge sensitive interrupt capability.
1.5.26
The MCF5253 has a primary and a secondary interrupt controller. These interrupt controllers handle
interrupts from all internal interrupt sources. In addition, there are 7 GPIOs where external interrupts can
be generated on the rising or falling edge of the pin. All interrupts are autovectored and interrupt levels are
programmable.
1.5.27
To help with system diagnostics and manufacturing testing, the MCF5253 includes dedicated
user-accessible test logic that complies with the IEEE 1149.1A standard for boundary scan testability,
often referred to as Joint Test Action Group, or JTAG. For more information, refer to the IEEE 1149.1A
standard. Freescale provides BSDL files for JTAG testing.
1.5.28
The ColdFire processor core debug interface supports real-time instruction trace and debug, plus
background-debug mode. A background-debug mode (BDM) interface provides system debug.
In real-time instruction trace, four status lines provide information on processor activity in real time (PST
pins). A four-bit wide debug data bus (DDATA) displays operand data and change-of-flow addresses,
which helps track the CPU’s dynamic execution path.
1.5.29
The oscillator will operate from an external crystal connected across CRIN and CROUT. The circuit can
also operate from an external clock connected to CRIN.
Typically, an external 16.92 MHz or 33.86 MHz clock input is used for CD R/W applications, while an
11.2896 MHz clock is more practical for Portable CD player applications. However, the on-chip
programmable PLL, which generates the processor clock, allows the use of almost any low frequency
external clock (5-35 MHz).
Two clock outputs (MCLK1 and MCLK2) are provided for use as Audio Master Clock. The output
frequencies of both outputs are programmable to Fxtal, Fxtal/2, Fxtal/3, and Fxtal/4. The Fxtal/3 option is
intended for use when the 33.86 MHz crystal option is used.
1-12
•
CS0 is intended to be used with an external boot ROM / Flash memory.
The MCF5253 can boot from its internal boot ROM, here CS0 is used internally, CS0/CS4 pin is
then is configured as CS4. CS0 and CS4 cannot be used simultaneously.
One dedicated chip select (CS2) is used for the IDE interface
GPIO Interface
Interrupt Controller
JTAG
System Debug Interface
System Oscillator and PLL
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor