MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 587

IC MPU 32BIT 140MHZ 225-MAPBGA

MCF5253CVM140

Manufacturer Part Number
MCF5253CVM140
Description
IC MPU 32BIT 140MHZ 225-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF525xr

Specifications of MCF5253CVM140

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
140MHz
Connectivity
CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
Peripherals
DMA, WDT
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
225-MAPBGA
Family Name
MCF5xxx
Device Core
ColdFire V2
Device Core Size
32b
Frequency (max)
140MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.2/3.3V
Operating Supply Voltage (max)
1.32/3.6V
Operating Supply Voltage (min)
1.08/3V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
225
Package Type
MA-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant

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24.10.2 Endpoint Transfer Descriptor (dTD)
The dTD describes to the device controller the location and quantity of data to be sent/received for given
transfer. The DCD should not attempt to modify any field in an active dTD except the Next Link Pointer,
which should only be modified as described in
Descriptors.”
Freescale Semiconductor
DWord
1
31
31–5
4–1
Bit
1
2
Device controller read/write; all others read-only.
00
0
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Next transfer element pointer. This field contains the physical memory address of the next dTD to be processed. The
field corresponds to memory address signals [31–5], respectively.
Reserved. Bits reserved for future use and should be cleared.
Terminate (T). 1=pointer is invalid. 0=Pointer is valid (points to a valid Transfer Element Descriptor). This bit indicates
to the Device Controller that there are no more valid entries in the queue.
31–0
31–0
Bits
Setup Buffer 0. This buffer contains bytes 3 to 0 of an incoming setup buffer packet and is written by the
device controller to be read by the software.
Setup Buffer 1. This buffer contains bytes 7 to 4 of an incoming setup buffer packet and is written by the
device controller to be read by the software.
Buffer Pointer (Page 0)
Buffer Pointer (Page 1)
Buffer Pointer (Page 2)
Buffer Pointer (Page 3)
Buffer Pointer (Page 4)
Total Bytes
Figure 24-62. Endpoint Transfer Descriptor (dTD)
1
Next Link Pointer
Table 24-76. Multiple Mode Control
MCF5253 Reference Manual, Rev. 1
Table 24-77. Next dTD Pointer
Section 24.11.5, “Managing Transfers with Transfer
ioc
15
Description
14 13 12 11 10
000
Description
MultO
0
9
00
8
0000_0000_0000
0000_0000_0000
0000_0000_0000
Current Offset
Frame Number
7
6
5
Universal Serial Bus Interface
Status
4
1
0000
3
1
1
2
1
T 0x00
0
Offset
0x0C
0x04
0x08
0x10
0x14
0x18
24-125

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