MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 253

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

TxD. If the transmitter is reset through a software command, operation ceases immediately (refer to
Section 15.4.5, “Command Registers
operation after a disable or software reset.
If clear-to-send operation is enabled, CTS
negated in the middle of a transmission, the character in the shift register is transmitted and following the
completion of STOP bits TxD, enters in the mark state until CTS is asserted again. If the transmitter is
forced to send a continuous low condition by issuing a Send-Break command, the transmitter ignores the
state of CTS.
Users can program the transmitter to automatically negate the request-to-send (RTS) output on completion
of a message transmission. If the transmitter is programmed to operate in this mode, RTS must be manually
asserted before a message is transmitted. In applications where the transmitter is disabled after
transmission is complete and RTS is appropriately programmed, RTS is negated one bit time after the
character in the shift register is completely transmitted. Users must manually enable the transmitter by
setting the enable-transmitter bit in the UART Command Register (UCR).
1. CTS and RTS are not available on UART2.
Freescale Semiconductor
TxD
Transmitter 4
Enabled
TxRDY
Internal
Module
Select
Notes:
1. Timing shown for UMR2[4]=1. not available on UART2
2. Timing shown for UMR2[5]=1. not available on UART2
3. CN=Transmit 8-bit character
4. Transmitter enable by configuring TCx bits in UCR (see
5. Start break/Stop break programmed by MISCx bits in UCR
6. Transmitter is enabled and disabled by using software control
RTS
CTS
(W=Write)
2
1
C1
W
Manually Asserted
by Bit-Set Command
C1
W
C2
Figure 15-5. Transmitter Timing Diagram
MCF5253 Reference Manual, Rev. 1
(UCRn)”). The transmitter is re-enabled through the UCR to resume
1
must be asserted for the character to be transmitted. If CTS is
C3
C2
W
Start5
Break
W
Table
C3
(seeTable
15-10)
C4
W
15-9)
Stop
Break Not
W
Transmitted
W
Disable
Trans.
C4
W
C5
7
Negated since transmit
buffer and shift register are
empty (last character has
been shifted out)
W
C6
Manually Asserted
C6
UART Modules
15-7