MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 100

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Static RAM (SRAM)
The RAMBAR register contains several control fields. These fields are detailed in the following tables.
6-2
Address
Address
Reset
Reset
Reset
Reset
•
•
•
•
W
W
W
W
R BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16
R
R
R
The RAMBAR register holds the base address of the SRAM. The MOVEC instruction provides
write-only access to this register.
The RAMBAR registers can be read or written from the Debug module in a similar manner.
All undefined bits in the register are reserved. These bits are ignored during writes to the
RAMBAR, and return zeroes when read from the debug module.
The RAMBAR valid bit is cleared by reset, disabling the SRAM module. All other bits are
unaffected.
CPU + $C04
CPU + $C05
BA15 BA14
BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16
BA15 BA14
31
15
31
15
–
–
–
–
All unused bits in the RAMBAR register must be initialized to zero
30
14
–
–
30
14
–
–
29
13
–
–
29
13
–
–
Figure 6-2. SRAM1 Base Address Register (RAMBAR1)
Figure 6-1. SRAM Base Address Register (RAMBAR0)
28
12
–
–
28
12
–
–
PRI1 PRI2
27
11
–
–
27
11
–
–
MCF5253 Reference Manual, Rev. 1
26
10
–
–
26
10
–
–
SPV
25
–
–
25
9
–
–
9
NOTE
WP
WP
24
24
–
–
8
–
–
8
23
23
–
7
–
–
–
7
22
22
–
–
6
–
6
–
C/I
C/I
21
21
–
–
–
–
5
5
SC
SC
20
20
–
–
–
–
4
4
SD
SD
19
19
–
–
–
–
3
3
Freescale Semiconductor
Access: User read/write
Access: User read/write
UC
UC
18
18
–
–
–
–
2
2
UD
UD
17
17
–
–
–
–
1
1
16
16
V
V
–
0
–
0
0
0