MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 639

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

The first write to the control/status word is important in case there was a pending reception or transmission.
The write operation immediately deactivates the MB, removing it from any currently ongoing arbitration
or matching process, giving time for the CPU to program the rest of the MB. Once the MB is activated in
the third step, it will be able to receive CAN frames that match the programmed ID. At the end of a
successful reception, the value of the free running timer (TIMER n ) is written into the time stamp field, the
received ID, data (8 bytes at most) and length fields are stored, the CODE field in the control and status
word is updated (see
generated if allowed by the corresponding IMASK n bit.
The CPU should read a receive frame from its MB by reading the following:
Upon reading the control and status word, if the BUSY bit is set in the CODE field, then the CPU should
defer the access to the MB until this bit is negated. Reading the free running timer is not mandatory. If not
executed the MB remains locked, unless the CPU reads the C/S word of another MB. Note that only a
single MB is locked at a time. The only mandatory CPU read operation is the one on the control and status
word to assure data coherency.
The CPU should synchronize to frame reception by an IFLAG n bit for the specific MB (see
“Interrupt Flag Register
the CODE field does not work because once a frame was received and the CPU services the MB (by
reading the C/S word followed by unlocking the MB), the CODE field will not return to EMPTY. It will
remain FULL, as explained in
C/S word to force an EMPTY code after reading the MB, the MB is actually deactivated from any currently
ongoing matching process. As a result, a newly received frame matching the ID of that MB may be lost.
In summary, never do polling by directly reading the C/S word of the MBs. Instead, read the IFLAG n
register.
Note that the received identifier field is always stored in the matching MB, thus the contents of the ID field
in an MB may change if the match was due to masking.
25.6.3.1
Self-received frames are frames that are sent by the FlexCAN and received by itself. The FlexCAN sends
a frame externally through the physical layer onto the CAN bus, and if the ID of the frame matches the ID
of the FlexCAN MB, then the frame will be received by the FlexCAN. Such a frame is a self-received
frame. Note that FlexCAN does not receive frames transmitted by itself if another device on the CAN bus
has an ID that matches the FlexCAN Rx MB ID.
Freescale Semiconductor
1. Control/status word (mandatory—activates internal lock for this buffer)
2. ID (optional—needed only if a mask was used)
3. Data field words
4. Free-running timer (Releases internal lock—optional)
Self-Received Frames
The first and last steps are mandatory.
Table
(IFLAGn)”), and not by the control/status word CODE field for that MB. Polling
25-12), and a status flag is set in the IFLAG n register and an interrupt is
Table
25-12. If the CPU tries to workaround this behavior by writing to the
MCF5253 Reference Manual, Rev. 1
NOTE
Section 25.5.8,
FlexCAN Module
25-23