MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 81

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 4
Phase-Locked Loop and Clock Dividers
This chapter provides detailed information about the operation and programming of the clock generation
module as well as the recommended circuit settings. It also describes the audio clock generation and the
system power states.
4.1
Figure 4-1
Freescale Semiconductor
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The PLL locks to the crystal clock at the CRIN pin and produces a processor clock (PSTCLK) and
a SYSCLK which is always 1/2 of the processor clock.
The audio clock (AUDIOCLK) can be derived directly from CRIN or from the
LRCK3/AUDIOCLK/GPIO43 input pin.
The Audio DAC Master clocks MCLK1 and MCLK2 are derived directly from CRIN.
The PLL is configured by writing to a configuration register.
The PLL Configuration Register must always be programmed to Bypass mode before it is
reprogrammed to change any clock frequency. In bypass mode, the crystal clock is fed to the
processor (PSTCLK).
When the PLL is switched from “bypass” to “normal operation”, the switch-over is delayed until
the PLL is locked.
The MCF5253 has a new block added to the output of the PLL / Clock Dividers to provide
glitch-free Dynamic Clock Switching. This allows dynamic switching of the clock rate being fed
to the CPU core and the system bus. This new block is controlled by a new 32-bit register called
the ClockRate Register.
PLL Features
shows the PLL module and the frequency relationships of various clock signals.
MCF5253 Reference Manual, Rev. 1
4-1