MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 403

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

commands. The PBMR is accessible in supervisor mode as debug control register $9 using the WDEBUG
instruction and through the BDM port using the WDMREG command.
ADDRESS[31:0]–PC Breakpoint Address
This field contains the 32-bit address to be compared with the PC as a breakpoint trigger.
MASK[31:0]–PC Breakpoint Mask
This field contains the 32-bit mask for the PC breakpoint trigger. A zero in a bit position causes the
corresponding bit in the PBR to be compared to the appropriate bit of the PC. A one causes that bit to be
ignored.
20.5.4
The data breakpoint registers (DBR and DBMR) define a specific data pattern that can be used as part of
the trigger into debug mode.The DBR value is masked by the DBMR value, allowing only those bits in
DBR that have a corresponding zero in DBMR to be compared with the data value from the processor’s
local bus, as defined in the TDR. The DBR is accessible in supervisor mode as debug control register $E
using the WDEBUG instruction and through the BDM port using the RDMREG and WDMREG
commands. The DBMR is accessible in supervisor mode as debug control register $F using the WDEBUG
instruction and through the BDM port using the WDMREG command. The DBR is overwritten by the
BDM hardware when accessing memory as described in
Freescale Semiconductor
Reset
Reset
Reset
Reset
W
W
W
W
R
R
R
R
31
15
31
15
–
–
–
–
Data Breakpoint Registers (DBR, DBMR)
30
14
30
14
–
–
–
–
Figure 20-33. Program Counter Breakpoint Mask Register (PBMR)
29
13
29
13
–
–
–
–
Figure 20-32. Program Counter Breakpoint Register (PBR)
28
12
28
12
–
–
–
–
27
11
27
11
–
–
–
–
MCF5253 Reference Manual, Rev. 1
26
10
26
10
–
–
–
–
25
25
–
–
–
–
9
9
ADDRESS[31:0]
ADDRESS[31:0]
MASK [31:0]]
MASK [31:0]
24
24
–
–
–
–
8
8
Section 20.4.1.2, “Debug Module Hardware.”
23
23
–
–
–
–
7
7
22
22
–
–
–
–
6
6
21
21
–
–
–
–
5
5
Background Debug Mode (BDM) Interface
20
20
–
–
–
–
4
4
19
19
–
–
–
–
3
3
Access: User write only
Access: User write only
18
18
–
2
–
–
2
–
17
17
–
–
–
–
1
1
20-33
16
16
–
–
–
–
0
0