MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 566

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Universal Serial Bus Interface
24.9.12.3.1 Split Transaction Scheduling Mechanisms for Isochronous
Full-speed isochronous transactions are managed through a transaction translator's periodic pipeline. As
with full- and low-speed interrupt, the system software manages each transaction translator's periodic
pipeline by budgeting and scheduling exactly during which micro-frames the start-splits and
complete-splits for each full-speed isochronous endpoint occur. The requirements described in
Section 24.9.12.2.1, “Split Transaction Scheduling Mechanisms for
illustrates the general scheduling boundary conditions that are supported by the EHCI periodic schedule.
The S
(respectively). The H-Frame boundaries are marked with a large, solid bold vertical line. The B-Frame
boundaries are marked with a large, bold, dashed line. The bottom of the figure illustrates the relationship
of an siTD to the H-Frame.
24-104
Periodic Schedule
Start & Complete
n
End of H-Frame
HS/FS/LS Bus
and C
Frame Wrap at
Micro-Frame 0
Micro-Frame
Micro-Frame
Normal Case
in H-Frame,
Case 2a:
Case 2b:
n
Case 1:
Figure 24-57. Split Transaction, Isochronous Scheduling Boundary Conditions
labels indicate micro-frames where the software can schedule start- and complete-splits
B-Frame N–1
7
6
0
7
S
C
S
S
0
6
1
0
S
MCF5253 Reference Manual, Rev. 1
1
2
1
C
S
C
2
0
0
3
2
H-Frame N
C
S
C
3
1
1
siTD
4
3
B-Frame N
x
OUT
IN
C
S
C
S
0
2
2
5
4
C
C
S
1
3
3
6
5
Interrupt”
C
S
C
2
0
4
7
6
C
C
S
1
3
5
apply.
IN
0
7
OUT
S
IN
C
C
2
6
H-Frame N+1
Freescale Semiconductor
Figure 24-57
siTD
1
0
C
3
B-Frame N+1
x+1