MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 528

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Universal Serial Bus Interface
24.8.7.1
The first DWord of an FSTN contains a link pointer to the next schedule object. This object can be of any
valid periodic schedule data type.
24.8.7.2
The second DWord of an FTSN node contains a link pointer to a queue head. If the T-bit in this pointer is
a zero, then this FSTN is a Save-Place indicator. Its Typ field must be set by the software to indicate the
target data structure is a queue head. If the T-bit in this pointer is set, then this FSTN is the Restore
indicator. When the T-bit is a one, the host controller ignores the Typ field.
24.9
The general operational model is for the USB modules in host mode is defined by the Enhanced Host
Controller Interface (EHCI) Specification. The EHCI specification describes the register-level interface
for a host controller for the USB Revision 2.0. It includes a description of the hardware/software interface
24-66
31–5 BPLP Back Path Link Pointer. This field contains the address of a Queue Head. This field corresponds to memory
31–5 NPLP Normal Path Link Pointer. This field contains the address of the next data object to be processed in the periodic
4–3
2–1
4–3
2–1
Bit
Bit
0
0
Name
Name
Typ
Typ
T
–
–
T
Host Operations
address signals [31–5], respectively.
Reserved. These bits must be written as 0s.
The software must ensure this field is set to indicate the target data structure is a Queue Head (01). Any other
value in this field yields undefined results.
Terminate.
0 Link Pointer is valid (that is, the host controller may use bits [31–5] (in combination with the CTRLDSSEGMENT
1 Link Pointer field is not valid (that is, the host controller must not use bits [31–5] (in combination with the
list and corresponds to memory address signals [31–5], respectively.
Reserved. These bits must be written as 0s.
This field indicates to the host controller whether the item referenced is a iTD/siTD, a QH or an FSTN. This allows
the host controller to perform the proper type of processing on the item after it is fetched.
00 iTD (isochronous transfer descriptor)
01 QH (queue head)
10 siTD (split transaction isochronous transfer descriptor)
11 FSTN (Frame Span Traversal Node)
Terminate.
0 Link Pointer is valid.
1 Link Pointer field is not valid.
FTSN Normal Path Pointer
FSTN Back Path Link Pointer
register if applicable) as a valid memory address). This value also indicates that this FSTN is a Save-Place
indicator.
CTRLDSSEGMENT register if applicable) as a valid memory address). This value also indicates that this FSTN
is a Restore indicator.
Table 24-61. FSTN Back Path Link Pointer
Table 24-60. FTSN Normal Path Pointer
MCF5253 Reference Manual, Rev. 1
Description
Description
Freescale Semiconductor