MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 258

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

UART Modules
15.3.4
Multidrop Mode
The UART can be programmed to operate in a wakeup mode for multidrop or multiprocessor applications.
Functional timing information for the multidrop mode is shown in
Figure
15-8. The mode is selected by
setting bits 3 and 4 in UART mode register 1 (UMR1). This mode of operation connects the master station
to several slave stations (maximum of 256). In this mode, the master transmits an address character
followed by a block of data characters targeted for one of the slave stations. The slave stations channel
receivers are disabled; however, they continuously monitor the data stream sent out by the master station.
When the master sends an address character, the slave receiver channel notifies its respective CPU by
setting the RxRDY bit in the USR and generating an interrupt (if programmed to do so). Each slave station
CPU then compares the received address to its station address and enables its receiver if it wants to receive
the subsequent data characters or block of data from the master station. Slave stations not addressed
continue to monitor the data stream for the next address character. Data fields in the data stream are
separated by an address character. After a slave receives a block of data, the slave station CPU disables the
receiver and reinitiates the process.
Figure 15-8. Multidrop Mode Timing Diagram
A transmitted character from the master station consists of a start bit, a programmed number of data bits,
an address/data (A/D) bit flag, and a programmed number of stop bits. The A/D bit identifies the type of
character being transmitted to the slave station. The character is interpreted as an address character if the
A/D bit is set or as a data character if the A/D bit is cleared. The polarity of the A/D bit is selected by
MCF5253 Reference Manual, Rev. 1
15-12
Freescale Semiconductor