MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 382

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Background Debug Mode (BDM) Interface
20.3.4
A command sequence diagram (see
bubble in the diagram represents a single 17-bit transfer across the bus. The top half in each bubble
corresponds to the data transmitted by the development system to the debug module; the bottom half
corresponds to the data returned by the debug module in response to the previous development system
commands. Command and result transactions are overlapped to minimize latency.
The cycle in which the command is issued contains the development system command mnemonic (in this
example, “read memory location”). During the same cycle, the debug module responds with either the
low-order results of the previous command or a command complete status (if no results were required).
During the second cycle, the development system supplies the high-order 16 bits of the memory address.
The debug module returns a “not ready” response unless the received command was decoded as
unimplemented, in which case the response data is the illegal command encoding. If an illegal command
response occurs, the development system should retransmit the command.
In the third cycle, the development system supplies the low-order 16 bits of a memory address. The debug
module always returns the “not ready” response in this cycle. At the completion of the third cycle, the
20-12
Commands Transmitted to the Debug Module
Responses from the Debug Module
Read (Long)
Command Sequence Diagram
???
The “not ready” response can be ignored unless a memory-referencing cycle
is in progress. Otherwise, the debug module can accept a new serial transfer
after 32 processor clock periods.
Command Code Transmitted During This Cycle
Results From Previous Command
Sequence Taken if Illegal Command
is Received by Debug Module
“Not Ready”
“Illegal”
MS Addr
XXX
Figure 20-7. Command Sequence Diagram
High-Order 16 Bits of Memory Address
Figure
MCF5253 Reference Manual, Rev. 1
Data Unused From
This Transfer
“Not Ready”
“Not Ready”
Next CMD
20-7) shows the serial bus traffic for each command. Each
LS Addr
Low-Order 16 Bits of Memory Address
NOTE
Read
Memory
Location
Non-Serial Related Activity
“Not Ready”
Sequence Taken if Bus
Error Occurs On
Memory Access
High and Low-Order
16 Bits of Results
MS Result
XXX
BERR
XXX
XXX
Sequence Taken If
Operation Has Not
Completed
Freescale Semiconductor
“Not Ready”
Next CMD
Next CMD
LS Result
Next
Command
Mode