MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 511

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

24.8.3
The format of an isochronous transfer descriptor is illustrated in
for high-speed isochronous endpoints. All other transfer types should use queue structures. Isochronous
TDs must be aligned on a 32-byte boundary.
24.8.3.1
The first DWord of an iTD is a pointer to the next schedule data structure.
Freescale Semiconductor
1
2
31–5 Link Pointer These bits correspond to memory address signals [31–5], respectively. This field points to another
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
4–3
Bit
Host controller read/write; all others read-only.
These fields may be modified by the host controller if the I/O field indicates an OUT.
Status
Status
Status
Status
Status
Status
Status
Status
1
1
1
1
1
1
1
1
Name
–
Isochronous (High-Speed) Transfer Descriptor (iTD)
Next Link Pointer
Isochronous Transaction Descriptor (iTD/siTD) or Queue Head (QH).
Reserved. These bits are reserved and their value has no effect on operation. The software should initialize
this field to zero.
Transaction 0 Length
Transaction 1 Length
Transaction 2 Length
Transaction 3 Length
Transaction 4 Length
Transaction 5 Length
Transaction 6 Length
Transaction 7 Length
Buffer Pointer (Page 0)
Buffer Pointer (Page 1)
Buffer Pointer (Page 2)
Buffer Pointer (Page 3)
Buffer Pointer (Page 4)
Buffer Pointer (Page 5)
Buffer Pointer (Page 6)
Figure 24-38. Isochronous Transaction Descriptor (iTD)
Table 24-38. Next Schedule Element Pointer
Next Link Pointer
MCF5253 Reference Manual, Rev. 1
1
1
1
1
1
1
1
1
ioc
ioc
ioc
ioc
ioc
ioc
ioc
ioc
15
14 13 12
PG
PG
PG
PG
PG
PG
PG
PG
Description
2
2
2
2
2
2
2
2
I/O
11
Figure
EndPt
10
9
24-38. This structure is used only
Transaction 0 Offset
Transaction 1 Offset
Transaction 2 Offset
Transaction 3 Offset
Transaction 4 Offset
Transaction 5 Offset
Transaction 6 Offset
Transaction 7 Offset
8
Maximum Packet Size
Reserved
R
7
Reserved
Reserved
Reserved
Reserved
6
Universal Serial Bus Interface
Device Address
5
4
00
3
2
2
2
2
2
2
2
2
2
Typ
1
Mult
T 0x00
0
0x0C
0x1C
0x2C
0x3C
Offset
0x04
0x08
0x10
0x14
0x18
0x20
0x24
0x28
0x30
0x34
0x38
24-49