MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 622

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

FlexCAN Module
Programming the FlexCAN control registers is typically done during system initialization, prior to the
FlexCAN becoming synchronized with the CAN bus. The configuration registers can be changed after
synchronization by halting the FlexCAN module. This is done when the user sets the CANMCR n [HALT]
bit. The FlexCAN responds by setting the CANMCR n [NOTRDY] bit.
25.5.1
CANMCR n defines global system configurations, such as the module operation mode and maximum
message buffer configuration. Most of the fields in this register can be accessed at any time, except the
MAXMB field, which should only be changed while the module is in freeze mode.
25-6
FlexCAN0
FlexCAN1
MBAR2
0x101C
0x201C
0x1020
0x2020
0x1028
0x2028
0x1030
0x2030
0x1080
0x2080
0x1180
0x2180
Offset
FlexCAN Configuration Register (CANMCRn)
Interrupt Mask Register (IMASKn)
Interrupt Flag Register (IFLAGn)
Message Buffers 0–31 (MB0–31)
Message Buffers 16–31 (MB16–31)
Error Counter Register (ERRCNTn)
Error and Status Register
(ERRSTATn)
The FlexCAN has no hard-wired protection against invalid bit/field
programming within its registers. Specifically, no protection is provided if
the programming does not meet CAN protocol requirements.
Register
Table 25-1. FlexCAN Memory Map (continued)
MCF5253 Reference Manual, Rev. 1
Width
(Bits)
4096
2048
32
32
32
32
NOTE
Affected
by Hard
Reset
N
N
Y
Y
Y
Y
Affected
by Soft
Reset
N
Y
Y
Y
Y
N
Access
R/W
R/W
R/W
R/W
R/W
R/W
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset Value
Freescale Semiconductor
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