MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 234

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Address MBAR + $300
DMA Controller
14.4.3
The destination address register (DAR) is a 32-bit register containing the address to which the DMA
controller module sends data during a transfer.
14-6
Reset
Reset
Address MBAR + $304
Reset
Reset
W
W
R
R
MBAR+ $340
MBAR + $380
MBAR + $3C0
SAR31 SAR30 SAR29 SAR28 SAR27 SAR26 SAR25 SAR24 SAR23 SAR22 SAR21 SAR20 SAR19 SAR18 SAR17 SAR16
SAR15 SAR14 SAR13 SAR12 SAR11 SAR10 SAR9
W
W
R
R
31
15
0
0
MBAR + $344
MBAR + $384
MBAR + $3C4
DAR31 DAR30 DAR29 DAR28 DAR27 DAR26 DAR25 DAR24 DAR23 DAR22 DAR21 DAR20 DAR19 DAR18 DAR17 DAR16
DAR15 DAR14 DAR13 DAR12 DAR11 DAR10
31
15
0
0
Destination Address Register
30
14
Only part of the on-chip SRAM can be accessed by the DMA. The memory
controlled by RAMBAR0 is not visible for DMA. The memory controlled
by RAMBAR1 is visible for DMA. As a result, the SAR or DAR address
range cannot be programmed to on-chip SRAM0 memory, since the on-chip
DMAs cannot access on-chip SRAM0 as a source or destination. They can
access SRAM1, however.
0
0
30
14
0
0
29
13
0
0
29
13
0
0
28
12
0
0
Figure 14-5. Destination Address Register (DAR)
28
12
0
0
Figure 14-4. Source Address Register (SAR)
27
11
0
0
27
11
0
0
MCF5253 Reference Manual, Rev. 1
26
10
0
0
26
10
0
0
DAR9
25
0
0
9
25
0
9
0
NOTE
SAR8
DAR8
24
24
0
8
0
0
0
8
SAR7
DAR7
23
23
0
0
0
7
7
0
DAR6
SAR6
22
0
0
6
22
0
0
6
DAR5
SAR5
21
0
0
5
21
0
5
0
DAR4
SAR4
20
0
0
4
20
0
0
4
DAR3
19
SAR3
0
0
3
Access: User read/write
19
Freescale Semiconductor
0
3
0
Access: User read/write
DAR2
18
0
2
0
SAR2
18
0
2
0
DAR1
17
0
1
0
SAR1
17
0
0
1
DAR0
16
0
0
0
SAR0
16
0
0
0