MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 492

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Address MBAR2 + 0x784
Universal Serial Bus Interface
24-30
31–30
27–26
PSPD
PFSC
Field
PTW
PTS
Reset
Reset
29
28
25
24
W
W
R
R
Reserved.
Port Transceiver Select. This register bit is used to control which parallel transceiver interface is selected.
00 On-Chip transceiver (UTMI+)
01 Reserved.
10 Reserved.
11 Reserved.
This bit is not defined in the EHCI specification.
Reserved.
Parallel Transceiver Width. This register bit is used to control the data bus width of the parallel transceiver interface.
This bit defaults to 1 after reset and is read only.
0 8-bit interface—[60 MHz] UTMI+ interface.
1 16-bit interface—[30 MHz] UTMI+ interface.
PTW is valid only for UTMI mode (PTS = 00).
This bit is not defined in the EHCI specification.
Port Speed. This read-only register field indicates the speed at which the port is operating.
This bit is not defined in the EHCI specification.
00 Full-speed
01 Low-speed
10 High-speed
11 Undefined
Port Force Full-speed Connect. This bit is used to disable the chirp sequence that allows the port to identify itself as a
HS port.
0 Allow the port to identify itself as High Speed.
1 Force the port to connect only at Full-speed.
This bit is not defined in the EHCI specification.
31
15
0
0
PTS
30
14
Table 24-27. Port Status and Control (PORTSC) Register Field Descriptions
0
0
PO
29
13
0
0
Figure 24-25. Port Status and Control (PORTSC) Register
PTW
PP
28
12
1
0
27
11
1
0
PSPD
LS
MCF5253 Reference Manual, Rev. 1
26
10
1
0
25
0
9
0
PFSC PHCD WKOC WKDS WLCN
Description
PR
24
0
8
0
SUSP
23
0
0
7
FPR
22
0
0
6
Clear
OCC
21
0
0
5
OCA
20
0
0
4
Clear
PEC
19
0
0
Freescale Semiconductor
3
Access: User read/write
PE
18
0
1
2
PTC
Clear
CSC
17
0
0
1
CCS
16
0
0
0