MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 71

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

3.5
3.5.1
The exact processor response to an access error depends on the type of memory reference being performed.
For an instruction fetch, the processor postpones the error reporting until the faulted reference is needed
by an instruction for execution. Therefore, faults that occur during instruction prefetches that are then
followed by a change of instruction flow do not generate an exception. When the processor attempts to
execute an instruction with a faulted opword and/or extension words, the access error is signaled and the
instruction aborted. For this type of exception, the programming model has not been altered by the
instruction generating the access error.
If the access error occurs on an operand read, the processor immediately aborts the current instruction’s
execution and initiates exception processing. In this situation, any address register updates attributable to
the auto-addressing modes, (e.g., (An)+,-(An)), have already been performed, so the programming model
contains the updated An value. In addition, if an access error occurs during the execution of a MOVEM
instruction loading from memory, any registers already updated before the fault occurs contains the
operands from memory.
The ColdFire processor uses an imprecise reporting mechanism for access errors on operand writes.
Because the actual write cycle may be decoupled from the processor’s issuing of the operation, the
signaling of an access error appears to be decoupled from the instruction that generated the write.
Accordingly, the PC contained in the exception stack frame merely represents the location in the program
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There is a 4-bit fault status field, FS[3:0], at the top of the system stack. This field is defined for
access and address errors only and written as zeros for all other types of exceptions. See
The 8-bit vector number, vector[7:0], defines the exception type and is calculated by the processor
for all internal faults and represents the value supplied by the peripheral in the case of an interrupt.
Refer to
Processor Exceptions
Access Error Exception
Table
3-5.
FS[3:0]
0100
0101
1000
1001
1100
1101
00xx
011x
101x
111x
Table 3-7. Fault Status Encoding
MCF5253 Reference Manual, Rev. 1
Attempted write to write-protected space
Error on instruction fetch
Error on operand write
Error on operand read
Definition
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ColdFire Core
Table
3-7.
3-9