MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 530

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Universal Serial Bus Interface
In order to communicate with devices via the asynchronous schedule, the system software must write the
ASYNDLISTADDR register with the address of a control or bulk queue head. The software must then
enable the asynchronous schedule by writing a one to the Asynchronous Schedule Enable bit in the
USBCMD register. In order to communicate with devices via the periodic schedule, the system software
must enable the periodic schedule by writing a one to the Periodic Schedule Enable bit in the USBCMD
register. Note that the schedules can be turned on before the first port is reset (and enabled).
Any time the USBCMD register is written, the system software must ensure the appropriate bits are
preserved, depending on the intended operation.
24.9.2
The Port Power Control (PPC) bit in the HCSPARAMS register indicates whether the USB 2.0 host
controller has port power control. When the PPC bit is a one, then the host controller supports port power
switches. Each available switch has an output enable. PPE is controlled based on the state of the
combination bits PPC bit, EHCI Configured (CF)-bit and individual Port Power (PP) bits.
24.9.3
Host ports by definition are power providers on USB. Whether the ports are considered high- or
low-powered is a platform implementation issue. Each EHCI PORTSC register has an over-current status
and over-current change bit. The functionality of these bits is specified in the USB Specification
Revision 2.0.
In this implementation, however, over-current is not reported to the USB core. Therefore the bits:
Over-current Active and Over-current Change in the PORTSC register will be static. The over-current
detection and limiting logic resides outside the MCF5253. The USB software stack is responsible for
monitoring the Over-current condition on the external device.
24.9.4
The host controller provides an equivalent suspend and resume model as that defined for individual ports
in a USB 2.0 hub. Control mechanisms are provided to allow the system software to suspend and resume
individual ports. The mechanisms allow the individual ports to be resumed completely via software
initiation. Other control mechanisms are provided to parameterize the host controller's response (or
sensitivity) to external resume events. In this discussion, host-initiated, or software-initiated resumes are
called Resume Events/Actions; bus-initiated resume events are called wake-up events. The classes of
wakeup events are:
Selective suspend is a feature supported by the PORTSC register. It is used to place specific ports into a
suspend mode. This feature is used as a functional component for implementing the appropriate power
24-68
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•
Remote-wakeup enabled device asserts resume signaling. In similar kind to USB 2.0 hubs, when
in host mode the host controller responds to explicit device resume signaling and wake up the
system (if necessary).
Port connect and disconnect. Sensitivity to these events can be turned on or off by using the port
control bits in the PORTSC register. An Over-current event will not wake the USB core.
Power Port
Reporting Over-Current
Suspend/Resume
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor