MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 537

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

24.9.8
The structure of an iTD is presented in Isochronous (High-Speed) Transfer Descriptor (iTD). There are
four distinct sections to an iTD:
24.9.8.1
The host controller uses FRINDEX register bits [12:3] to index into the periodic frame list. This means
that the host controller visits each frame list element eight consecutive times before incrementing to the
next periodic frame list element. Each iTD contains eight transaction descriptions, which map directly to
FRINDEX register bits [2:0]. Each iTD can span 8 micro-frames worth of transactions. When the host
controller fetches an iTD, it uses FRINDEX register bits [2:0] to index into the transaction description
array. If the active bit in the Status field of the indexed transaction description is cleared, the host controller
ignores the iTD and follows the Next pointer to the next schedule data structure.
When the indexed active bit is a one the host controller continues to parse the iTD. It stores the indexed
transaction description and the general endpoint information (device address, endpoint number, maximum
Freescale Semiconductor
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The first field is the Next Link Pointer. This field is for schedule linkage purposes only.
Transaction description array. This area is an eight-element array. Each element represents control
and status information for one micro-frame's worth of transactions for a single high-speed
isochronous endpoint.
The buffer page pointer array is a 7-element array of physical memory pointers to data buffers.
These are 4K aligned pointers to physical memory.
Endpoint capabilities. This area utilizes the unused low-order 12 bits of the buffer page pointer
array. The fields in this area are used across all transactions executed for this iTD, including
endpoint addressing, transfer direction, maximum packet size and high-bandwidth multiplier.
1024, 512, or 256
Managing Isochronous Transfers Using iTDs
Host Controller Operational Model for iTDs
Elements
Periodic Frame List
Figure 24-47. Example Periodic Schedule
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MCF5253 Reference Manual, Rev. 1
Poll Rate: 1
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A
A
A
A
A
A
Poll Rate: N –– > 1
8
Isochronous Transfer
Descriptor(s)
A
4
• • •
1
Last
Periodic has
End of
List Mark
Universal Serial Bus Interface
Interrupt Queue
Heads
24-75