MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 411

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 21
IEEE 1149.1 Test Access Port (JTAG)
This chapter discussed the JTAG signal descriptions, TAP controller, register descriptions, and how to
disable the standard operation.
The MCF5253 JTAG test architecture implementation currently supports circuit board test strategies that
are based on the IEEE standard. This architecture provides access to all of the data and chip control pins
from the board edge connector through the standard four-pin test access port (TAP) and the active-low
JTAG reset pin, TRST. The test logic uses static design and is wholly independent of the system logic,
except where the JTAG is subordinate to other complimentary test modes (see
Debug Mode (BDM)
placed in reset and the TAP pins can be used for other purposes in accordance with the rules and
restrictions set forth using a JTAG compliance-enable pin.
21.1
The MCF5253 JTAG implementation can do the following:
21.2
Figure 21-1
logic includes several test data registers, an instruction register, instruction register control decode, and a
16-state dedicated TAP controller.
Freescale Semiconductor
•
•
•
•
•
Perform boundary-scan operations to test circuit board electrical continuity
Bypass the MCF5253 by reducing the shift register path to a single cell
Sample the MCF5253 system pins during operation and transparently shift out the result
Set the MCF5253 output drive pins to fixed logic values while reducing the shift register path to a
single cell
Protect the MCF5253 system output and input pins from backdriving and random toggling (such
as during in-circuit testing) by placing all system signal pins to high- impedance state
Features
Block Diagram
is a block diagram of the MCF5253 implementation of the 1149.1A IEEE Standard. The test
The IEEE Standard 1149.1 test logic cannot be considered completely
benign to those planning not to use JTAG capability. Users must observe
certain precautions to ensure that this logic does not interfere with system or
debug operation. Refer to
Operation.”
Interface,”
for more information). When in subordinate mode, the JTAG test logic is
MCF5253 Reference Manual, Rev. 1
Section 21.7, “Disabling IEEE 1149.1A Standard
NOTE
Chapter 20, “Background
21-1