MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 540

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Universal Serial Bus Interface
As noted above, the client request includes a pointer to the base of the buffer and offsets into the buffer to
annotate which buffer sections are to be used on each bus transaction that occurs on this endpoint. The
system software must initialize each transaction description in an iTD to ensure it uses the correct portion
of the client buffer. For example, for each transaction description, the PG field is set to index the correct
physical buffer page pointer and the Transaction Offset field is set relative to the correct buffer pointer
page (for example, the same one referenced by the PG field). When the host controller executes a
transaction it selects a transaction description record based on FRINDEX[2:0]. It then uses the current
Page Buffer Pointer (as selected by the PG field) and concatenates to the transaction offset field. The result
is a starting buffer address for the transaction. As the host controller moves data for the transaction, it must
watch for a page wrap condition and properly advance to the next available Page Buffer Pointer. The
system software must not use the Page 6 buffer pointer in a transaction description where the length of the
transfer will wrap a page boundary. Doing so yields undefined behavior. The host controller hardware is
not required to alias the page selector to page zero. USB 2.0 isochronous endpoints can specify a period
greater than one. The software can achieve the appropriate scheduling by linking iTDs into the appropriate
frames (relative to the frame list) and by setting appropriate transaction description elements active bits to
a one.
24.9.8.2.1
The Isochronous Scheduling Threshold field in the HCCPARAMS capability register is an indicator to the
system software as to how the host controller pre-fetches and effectively caches schedule data structures.
It is used by the system software when adding isochronous work items to the periodic schedule. The value
of this field indicates to the system software the minimum distance it can update isochronous data (relative
to the current location of the host controller execution in the periodic list) and still have the host controller
process them.
24-78
Frame List
Frame i+1
Frame i+2
Frame i+n
Frame i
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Periodic Scheduling Threshold
Figure 24-48. Example Association of iTDs to Client Request Buffer
MCF5253 Reference Manual, Rev. 1
iTD
iTD
iTD
N
0
1
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Client Buffer
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Freescale Semiconductor
Transaction
Information
Request
Client
USB