R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 97

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 3.3
Note: No FPU error occurs in the SH2A-FPU.
3.3.3
Information is transferred between the FPU and CPU via FPUL. FPUL is a 32-bit system register
that is accessed from the CPU side by means of LDS and STS instructions. For example, to
convert the integer stored in general register R1 to a single-precision floating-point number, the
processing flow is as follows:
Bit
17 to 12
11 to 7
6 to 2
1
0
Field Name
Cause
Enable
Flag
R1 → (LDS instruction) → FPUL → (single-precision FLOAT instruction) → FR1
Floating-Point Communication Register (FPUL)
FPU exception
cause field
FPU exception
enable field
FPU exception flag
field
Bit Name
Cause
Enable
Flag
RM1
RM0
Bit Allocation for FPU Exception Handling
Initial
Value
All 0
All 0
All 0
0
1
FPU
Error (E)
Bit 17
None
None
R/W
R/W
R/W
R/W
R/W
R/W
Invalid
Operation (V)
Bit 16
Bit 11
Bit 6
Description
FPU Exception Cause Field
FPU Exception Enable Field
FPU Exception Flag Field
When an FPU exception occurs, the bits corresponding
to the FPU exception cause field and FPU exception
flag field are set to 1. Each time an FPU operation
instruction is executed, the FPU exception cause field
is cleared to 0. The FPU exception flag field remains
set to 1 until it is cleared to 0 by software.
For bit allocations of each field, see table 3.3.
Rounding Mode
These bits select the rounding mode.
00: Round to Nearest
01: Round to Zero
10: Reserved
11: Reserved
Division
by Zero (Z)
Bit 15
Bit 5
Bit 10
Rev. 2.00 Sep. 07, 2007 Page 69 of 1164
Section 3 Floating-Point Unit (FPU)
Overflow
(O)
Bit 14
Bit 9
Bit 4
Underflow
(U)
Bit 13
Bit 8
Bit 3
REJ09B0321-0200
Bit 12
Bit 7
Bit 2
Inexact
(I)