R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 531
R5S72011
Manufacturer Part Number
R5S72011
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5S72011.pdf
(1196 pages)
- Current page: 531 of 1196
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Positive phase
output
Negative phase
output
Timer output control register settings
OLSN bit: 0 (initial output: high; active level: low)
OLSP bit: 0 (initial output: high; active level: low)
Figure 12.45 Example of Initial Output in Complementary PWM Mode (2)
Complementary
PWM mode
(TMDR setting)
Initial output
TGRA_4
TCNT_3 and TCNT_4 values
TDDR
TCNT_3 and TCNT_4 count start
(TSTR setting)
Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Rev. 2.00 Sep. 07, 2007 Page 503 of 1164
TCNT_3
TCNT_4
Active level
REJ09B0321-0200
Time
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