R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 202

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 User Break Controller (UBC)
6. When selecting the I bus as the break condition, note as follows:
7.4.2
1. When C bus/instruction fetch/read/word or longword is set in the break bus cycle register
2. A break for instruction fetch which is set as a break before instruction execution occurs when it
3. When setting a break condition for break after instruction execution, the instruction set with
4. When an instruction fetch cycle is set, the break data register (BDR) is ignored. Therefore,
5. If the I bus is set for a break of an instruction fetch cycle, the setting is invalidated.
Rev. 2.00 Sep. 07, 2007 Page 174 of 1164
REJ09B0321-0200
 Whether or not the access the CPU issued on the C bus is issued on the I bus depends on
 When a break condition is specified for the I bus, only the data access cycle is monitored.
 If a break condition is specified for the I bus, even when the condition matches in an I bus
(BBR), the break condition is the FAB bus instruction fetch cycle. Whether a start of user
break interrupt exception processing is set before or after the execution of the instruction can
be selected with the PCB0 or PCB1 bit in the break control register (BRCR) for the
appropriate channel. If an instruction fetch cycle is set as a break condition, clear LSB in the
break address register (BAR) to 0. A break cannot be generated as long as this bit is set to 1.
is confirmed that the instruction has been fetched and will be executed. This means a break
does not occur for instructions fetched by overrun (instructions fetched at a branch or during
an interrupt transition, but not to be executed). When this kind of break is set for the delay slot
of a delayed branch instruction, the user break interrupt request is not received until the
execution of the first instruction at the branch destination.
the break condition is executed and then the break is generated prior to execution of the next
instruction. As with pre-execution breaks, a break does not occur with overrun fetch
instructions. When this kind of break is set for a delayed branch instruction and its delay slot,
the user break interrupt request is not received until the first instruction at the branch
destination.
break data cannot be set for the break of the instruction fetch cycle.
Note: If a branch does not occur at a delayed branch instruction, the subsequent instruction is
the setting of the cache. As regard to the I bus operation that depends on cache conditions,
see table 8.8 in section 8, Cache.
The instruction fetch cycle (including cache update cycle) is not monitored.
cycle resulting from an instruction executed by the CPU, at which instruction the break is
to be accepted cannot be clearly defined.
Break on Instruction Fetch Cycle
not recognized as a delay slot.