R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 648

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 13 8-Bit Timers (TMR)
Notes: 1. Includes switching from low to stop, and from stop to low.
13.8.7
If 16-bit counter mode and compare match count mode are specified at the same time, input clocks
for TCNT_0 and TCNT_1 are not generated, and the counter stops. Do not specify 16-bit counter
mode and compare match count mode simultaneously.
13.8.8
Operation of the TMR can be disabled or enabled using the standby control register. The initial
setting is for operation of the TMR to be halted. Register access is enabled by clearing module
standby mode. For details, see section 25, Power-Down Modes.
13.8.9
If module standby mode is entered when an interrupt has been requested, it will not be possible to
clear the CPU interrupt source. Interrupts should therefore be disabled before entering module
standby mode.
Rev. 2.00 Sep. 07, 2007 Page 620 of 1164
REJ09B0321-0200
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2. Includes switching from stop to high.
3. Includes switching from high to stop.
4. Generated because the change of the signal levels is considered as a falling edge;
Mode Setting with Cascaded Connection
Module Standby Setting
Interrupts in Module Standby Mode
Timing to Change CKS1
and CKS0 Bits
Switching from high to high
TCNT is incremented.
TCNT Clock Operation
Clock before
switchover
Clock after
switchover
TCNT input
clock
TCNT
N
N + 1
CKS bits changed
N + 2