R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 130

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 5 Exception Handling
5.3.2
When an address error occurs, address error exception handling starts after the bus cycle in which
the address error occurred ends and execution of the instruction being executed completes. The
CPU operates as follows.
1. The exception service routine start address which corresponds to the address error that
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
4. After jumping to the address fetched from the exception handling vector table, program
5.4
5.4.1
In bus monitor, notification of bus error occurrence to the CPU can be set. The notification is
generated when incorrect address access or bus timeout is detected. For details, see section 10,
Bus Monitor.
5.4.2
When a bus error occurs, bus error exception handling starts after the bus cycle in which the bus
error occurred ends and execution of the instruction being executed completes. The CPU operates
as follows.
1. The exception service routine start address which corresponds to the bus error that occurred is
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
4. After jumping to the address fetched from the exception handling vector table, program
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occurred is fetched from the exception handling vector table.
instruction to be executed after the last executed instruction.
execution starts. The jump that occurs is not a delayed branch.
fetched from the exception handling vector table.
instruction to be executed after the last executed instruction.
execution starts. The jump that occurs is not a delayed branch.
Address Error Exception Handling
Bus Error
Bus Error Generation Source
Bus Error Exception Handling