R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 550

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Rev. 2.00 Sep. 07, 2007 Page 522 of 1164
REJ09B0321-0200
Bit BTE0 in TBTER
Bit BTE1 in TBTER
Buffer register
Temporary register
General register
[Legend]
(1) No data is transferred from the buffer register to the temporary register in the buffer transfer-disabled period
(2) Data is transferred from the temporary register to the general register even in the buffer transfer-disabled period.
(3) After buffer transfer is enabled, data is transferred from the buffer register to the temporary register.
Note: * When buffer transfer at the crest is selected.
(bits BTE1 and BTE0 in TBTER are set to 0 and 1, respectively).
Figure 12.70 Example of Operation when Buffer Transfer is Suppressed
data1
Data1
TCNT_3
Buffer transfer is suppressed
TCNT_4
(1)
Data*
Data*
(BTE1 = 0 and BTE0 = 1)
(2)
(3)
Data2
Data2
Data2