R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 482

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.3.31 Timer Waveform Control Register (TWCR)
TWCR is an 8-bit readable/writable register that controls the waveform when synchronous counter
clearing occurs in TCNT_3 and TCNT_4 in complementary PWM mode and specifies whether to
clear the counters at TGRA_3 compare match. The CCE bit and WRE bit in TWCR must be
modified only while TCNT stops.
Rev. 2.00 Sep. 07, 2007 Page 454 of 1164
REJ09B0321-0200
Bit
7
6 to 1
Bit Name
CCE
—
Note:
Initial value:
Initial
Value
0*
All 0
*
R/W:
Do not set to 1 when complementary PWM mode is not selected.
Bit:
R/(W)
CCE
0*
7
R/W
R/(W)
R
—
R
6
0
Description
Compare Match Clear Enable
Specifies whether to clear counters at TGRA_3
compare match in complementary PWM mode.
0: Does not clear counters at TGRA_3 compare match
1: Clears counters at TGRA_3 compare match
[Setting condition]
•
Reserved
These bits are always read as 0. The write value should
always be 0.
—
R
5
0
When 1 is written to CCE after reading CCE = 0
—
R
4
0
—
R
3
0
—
R
2
0
—
R
1
0
R/(W)
WRE
0
0